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Si5365
P R E L I M I N A R Y DA TA S H E E T
PI N - PROGRAMMABLE PR E C I S I O N C L O C K MU L T I P L I E R
Description
The Si5365 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel, in which the application requires clock multiplication without jitter attenuation. The Si5365 accepts four clock inputs ranging from 19.44 to 707 MHz and generates five frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5365 is based on Silicon Laboratories' 3rdgeneration DSPLL(R) technology, which provides anyrate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the Si5365 is ideal for providing clock multiplication in high performance timing applications.
Features
Selectable output frequencies ranging from 19.44 to 1050 MHz Low jitter clock outputs w/jitter generation as low as 0.6 ps rms (50 kHz-80 MHz) Integrated loop filter with selectable loop bandwidth (30 kHz to 1.3 MHz) Four clock inputs w/manual or automatically controlled hitless switching Five clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOS alarm outputs Digitally-controlled output phase adjust Pin-programmable settings On-chip voltage regulator for 1.8 or 2.5 V 10% operation Small size: 14 x 14 mm 100-pin TQFP Pb-free, RoHS compliant
Applications
SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 line cards Test and measurement
CKIN1 CKIN2 CKIN3 CKIN4
/ N31 / N32 / N33 / N34 / N2 / NC3 CKOUT3
/ NC1
CKOUT1
DSPLL
(R)
/ NC2
CKOUT2
Divider Select
Manual/Auto Switch Clock Select LOS/FOS Alarms Frequency Select Bandwidth Select Control / NC5 CKOUT5 VDD (1.8 or 2.5 V) GND / NC4 CKOUT4
Preliminary Rev. 0.34 3/07
Copyright (c) 2007 by Silicon Laboratories
Si5365
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5365
Table 1. Performance Specifications
(VDD = 1.8 or 2.5 V 10%, TA = -40 to 85 C)
Parameter Temperature Range Supply Voltage Supply Current
Symbol TA VDD IDD
Test Condition
Min -40 2.25 1.62
Typ 25 2.5 1.8 394
Max 85 2.75 1.98 435
Unit C V V mA
fOUT = 622.08 MHz All CKOUTs enabled LVPECL format output Only CKOUT1 enabled fOUT = 19.44 MHz All CKOUTs enabled CMOS format output Only CKOUT1 enabled Tristate/Sleep Mode
--
-- --
253 278
284 321
mA mA
-- -- 19.44
229 TBD --
261 TBD 707.35
mA mA MHz
Input Clock Frequency (CKIN1, CKIN2, CKIN3, CKIN4) Output Clock Frequency (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5)
CKF
CKOF
Input frequency and clock multiplication ratio pinselectable from table of values using FRQSEL and FRQTBL settings. Consult Silicon Laboratories configuration software DSPLLsim or Any-Rate Precision Clock Family Reference Manual at www.silabs.com/timing for table selections.
19.44
--
1049.76
MHz
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4) Differential Voltage Swing Common Mode Voltage Rise/Fall Time Duty Cycle CKNDPP CKNVCM CKNTRF CKNDC 1.8 V 10% 2.5 V 10% 20-80% Whichever is less 0.25 0.9 1.0 -- 40 50 Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5) Common Mode Differential Output Swing Single Ended Output Swing Rise/Fall Time VOCM VOD VSE CKOTRF LVPECL 100 load line-to-line VDD - 1.42 1.1 0.5 -- -- -- -- 230 VDD - 1.25 1.9 0.93 350 V V V ps -- -- -- -- -- -- 1.9 1.4 1.7 11 60 -- VPP V V ns % ns
20-80%
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
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Si5365
Table 1. Performance Specifications (Continued)
(VDD = 1.8 or 2.5 V 10%, TA = -40 to 85 C)
Parameter Duty Cycle PLL Performance Jitter Generation
Symbol CKODC JGEN
Test Condition
Min 45
Typ -- 0.6
Max 55 TBD
Unit % ps rms
fOUT = 622.08 MHz, LVPECL output format 50 kHz-80 MHz 12 kHz-20 MHz
--
-- --
0.6 0.05 TBD TBD TBD TBD TBD TBD TBD
TBD 0.1 TBD TBD TBD TBD TBD TBD TBD
ps rms dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc
Jitter Transfer Phase Noise
JPK CKOPN fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset
-- -- -- -- -- -- --
Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient
SPSUBH SPSPUR
Phase Noise @ 100 kHz Offset Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) Still Air
JA
--
40
--
C/W
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Table 2. Absolute Maximum Ratings
Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 k) ESD MM Tolerance Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value -0.5 to 2.75 -0.3 to (VDD + 0.3) -55 to 150 -55 to 150 2 200 JESD78 Compliant Unit V V C C kV V
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.34
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Si5365
155.52 MHz in, 622.08 MHz out
0 -20 Phase Noise (dBc/Hz) -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz)
Figure 1. Typical Phase Noise Plot
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Si5365
System Power Supply C10 Ferrite Bead 1 F C1-9 0.1 F VDD GND VDD = 3.3 V
130
130 CKIN1+
CKOUT1+
0.1 F 100
+
CKOUT1- CKIN1- 82 82
0.1 F
-
Input Clock Sources1
VDD = 3.3 V
Clock Outputs
130
130 CKIN4+ CKIN4- CKOUT5+ 0.1 F 100 CKOUT5- 0.1 F - +
82
82
Si5365
Manual/Automatic Clock Selection (L) Input Clock Select Frequency Table Select Frequency Select Bandwidth Select Signal Format Select CKOUT_3 and CKOUT_4 Divider Control Clock Output 2 Disable/ Bypass Mode Control Clock Outputs 3 and 4 Disable CKOUT5 Disable Reset AUTOSEL2 CKSEL[1:0]3 FRQTBL2 FRQSEL[3:0]2 BWSEL[1:0]2 SFOUT[1:0]2 DIV34[1:0]2 DBL2_BY2 DBL34 DBL52 RST ALRMOUT CnB Alarm Output Indicator CKIN_n Invalid Indicator (n = 1 to 3)
Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). 3. Assumes manual input clock selection.
Figure 2. Si5365 Typical Application Circuit
Preliminary Rev. 0.34
5
Si5365
1. Functional Description
The Si5365 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel, in which the application requires clock multiplication without jitter attenuation. The Si5365 accepts four clock inputs ranging from 19.44 to 707 MHz and generates five frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. By default the four clock inputs are at the same frequency and the five clock outputs are at the same frequency. Two of the output clocks can be divided down further to generate an integer sub-multiple frequency. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. In addition to providing clock multiplication in SONET and datacom applications, the Si5365 supports SONET-to-datacom frequency translations. Silicon Laboratories offers a PCbased software utility, DSPLLsim, that can be used to look up valid Si5365 frequency translations. This utility can be downloaded from www.silabs.com/timing. This information is also available in the Any-Rate Precision Clock Family Reference Manual, also available from www.silabs.com/timing. The Si5365 is based on Silicon Laboratories' 3rdgeneration DSPLL(R) technology, which provides anyrate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5365 PLL loop bandwidth is digitally programmable via the BWSEL[1:0] pins and supports a range from 30 kHz to 1.3 MHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5365 monitors all input clocks for loss-of-signal and provides a LOS alarm when it detects a missing clock. In the case when the input clocks enter alarm conditions, the PLL will freeze the DCO output frequency near its last value to maintain operation with an internal state close to the last valid operating state. The Si5365 has five differential clock outputs. The signal format of the clock outputs is programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, unused clock outputs can be powered down to minimize power consumption. The phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8 or 2.5 V supply.
1.1. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for more detailed information about the Si5365. The FRM can be downloaded from www.silabs.com/timing. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. This utility can be downloaded from www.silabs.com/timing.
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Si5365
2. Pin Descriptions: Si5365
VDD CKOUT4+ CKOUT2+ CKOUT5+ CKOUT1+ CKOUT3+ CKOUT4- CKOUT2- CKOUT5- VDD CKOUT1- CKOUT3- SFOUT0 VDD SFOUT1 DSBL34
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC NC RST FRQTBL VDD VDD GND GND C1B C2B C3B ALRMOUT CS0_C3A GND VDD GND NC GND GND NC NC AUTOSEL NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 74 73 72 71 70 69 68 67 66 65 64
VDD
NC
NC NC NC NC FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 DIV34_1 DIV34_0 GND GND VDD VDD BWSEL1 BWSEL0 C2A C1A CS1_C4A GND NC NC NC NC GND
Si5365
GND PAD
63 62 61 60 59 58 57 56 55 54 53 52
51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CKIN4- DBL2_BY CKIN1- GND CKIN4+ CKIN2+ CKIN3+ CKIN1+ CKIN3- CKIN2- DBL5 GND GND GND GND GND GND GND VDD VDD VDD NC NC NC
GND
Table 3. Si5365 Pin Descriptions
Pin # 1, 2, 17, 20, 21, 23, 24, 25, 47, 48, 49, 52, 53, 54, 55, 72, 73, 74, 75, 90 Pin Name NC I/O Signal Level Description No Connect. These pins must be left unconnected for normal operation.
Preliminary Rev. 0.34
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Si5365
Table 3. Si5365 Pin Descriptions (Continued)
Pin # 3 Pin Name RST I/O Signal Level I LVCMOS Description External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are tristated during reset. After rising edge of RST signal, the device will perform an internal self-calibration. This pin has a weak pull-up. Frequency Table Select. This pin selects SONET/SDH, datacom, or SONET/SDH to datacom frequency translation table. L = SONET/SDH. M = Datacom. H = SONET/SDH to Datacom. This pin has a weak pull-down. VDD. The device operates from a 1.8 or 2.5 V supply. Bypass capacitors should be associated with the following VDD pins: Pins Bypass Cap 5, 6 0.1 F 15 0.1 F 27 0.1 F 62, 63 0.1 F 76, 79 1.0 F 81, 84 0.1 F 86, 89 0.1 F 91, 94 0.1 F 96, 99, 100 0.1 F Ground. These pins must be connected to system ground. Minimize the ground path impedance for optimal performance.
4
FRQTBL
I
3-Level
5, 6, 15, 27, 32, 42, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100
VDD
VDD
Supply
7, 8, 14, 16, 18, 19, 26, 28, 31, 33, 36, 38, 41, 43, 46, 51, 56, 64, 65 9
GND
GND
Supply
C1B
O
LVCMOS
CKIN1 Invalid Indicator. This pin is an active high alarm output associated with CKIN1. Once triggered, the alarm will remain high until CKIN1 is validated. 0 = No alarm on CKIN1. 1 = Alarm on CKIN1. CKIN2 Invalid Indicator. This pin is an active high alarm output associated with CKIN2. Once triggered, the alarm will remain high until CKIN2 is validated. 0 = No alarm on CKIN2. 1 = Alarm on CKIN2. CKIN3 Invalid Indicator. This pin is an active high alarm output associated with CKIN3. 0 = No alarm on CKIN3. 1 = Alarm on CKIN3.
10
C2B
O
LVCMOS
11
C3B
O
LVCMOS
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Preliminary Rev. 0.34
Si5365
Table 3. Si5365 Pin Descriptions (Continued)
Pin # 12 Pin Name ALRMOUT I/O Signal Level O LVCMOS Description Alarm Output Indicator. This pin is an active high alarm output associated with CKIN4 or the frame sync alignment alarm. 0 = ALRMOUT not active. 1 = ALRMOUT active. Input Clock Select/CKINn Active Clock Indicator. If manual clock selection mode is chosen (AUTOSEL = 1), the CS[1:0] pins function as the manual input clock selector control. CS[1:0] 00 01 10 11 Active Input Clock CKIN1 CKIN2 CKIN3 CKIN4
13 57
CS0_C3A CS1_C4A
I/O
LVCMOS
These inputs are internally deglitched to prevent inadvertent clock switching during changes in the CSn input state. If automatic clock detection is chosen (AUTOSEL = M or H), these pins function as the CKINn active clock indicator output. 0 = CKINn is not the active input clock. 1 = CKINn is currently the active input clock to the PLL. This pin has a weak pull-down. 22 AUTOSEL I 3-Level Manual/Automatic Clock Selection. Three level input that selects the method of input clock selection to be used. L = Manual. M = Automatic non-revertive. H = Automatic revertive. Clock Input 4. Differential clock input. This input can also be driven with a single-ended signal. Clock Input 2. Differential input clock. This input can also be driven with a single-ended signal. CKOUT2 Disable/PLL Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode. L = CKOUT2 Enabled. M = CKOUT2 Disabled. H = BYPASS Mode with CKOUT2 enabled. Clock Input 3. Differential clock input. This input can also be driven with a single-ended signal. Clock Input 1. Differential clock input. This input can also be driven with a single-ended signal.
29 30 34 35 37
CKIN4+ CKIN4- CKIN2+ CKIN2- DBL2_BY
I
MULTI
I
MULTI
I
3-Level
39 40 44 45
CKIN3+ CKIN3- CKIN1+ CKIN1-
I
MULTI
I
MULTI
Preliminary Rev. 0.34
9
Si5365
Table 3. Si5365 Pin Descriptions (Continued)
Pin # 50 Pin Name DBL5 I/O Signal Level I 3-Level Description CKOUT5 Disable. This pin performs the following functions: L = Normal operation. Output path is active and signal format is determined by SFOUT inputs. M = CMOS signal format. Overrides SFOUT signal format to allow CKOUT5 to operate in CMOS format while the clock outputs operate in a differential output format. H = Powerdown. Entire CKOUT5 divider and output buffer path is powered down. CKOUT5 output will be in tristate mode during powerdown. CKIN1 Active Clock Indicator. This pin serves as the CKIN1 active clock indicator. 0 = CKIN1 is not the active input clock. 1 = CKIN1 is currently the active input clock to the PLL. CKIN2 Active Clock Indicator. This pin serves as the CKIN2 active clock indicator. 0 = CKIN2 is not the active input clock. 1 = CKIN2 is currently the active input clock to the PLL. Bandwidth Select. These pins are three level inputs that select the DSPLL closed loop bandwidth according to the Any-Rate Precision Clock Family Reference Manual. CKOUT3 and CKOUT4 Divider Control. These pins control the division of CKOUT3 and CKOUT4 relative to the CKOUT2 output frequency. Detailed operations and timing characteristics for these pins may be found in the Any-Rate Precision Clock Family Reference Manual. Multiplier Select. These pins are three level inputs that select the input clock and clock multiplication setting according to the Any-Rate Precision Clock Family Reference Manual, depending on the FRQTBL setting. Clock Output 3. Differential output clock with a frequency specified by FRQSEL and FRQTBL settings. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs.
58
C1A
O
LVCMOS
59
C2A
O
LVCMOS
60 61
BWSEL0 BWSEL1
I
3-Level
66 67
DIV34_0 DIV34_1
I
3-Level
68 69 70 71 77 78
FRQSEL0 FRQSEL1 FRQSEL2 FRQSEL3 CKOUT3+ CKOUT3-
I
3-Level
O
MULTI
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Preliminary Rev. 0.34
Si5365
Table 3. Si5365 Pin Descriptions (Continued)
Pin # 80 95 Pin Name SFOUT1 SFOUT0 I/O Signal Level I 3-Level Description Signal Format Select. Three level inputs that select the output signal format (common mode voltage and differential swing) for all of the clock outputs and CKOUT5. SFOUT[1:0] HH HM HL MH MM ML LH LM LL 82 83 CKOUT1- CKOUT1+ O MULTI Signal Format Reserved Reserved CML LVPECL Reserved LVDS CMOS Tristate/Sleep Reserved
Clock Output 1. Differential output clock with a frequency specified by FRQSEL and FRQTBL. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Output 3 and 4 Disable. Active high input. When active, entire CKOUT3 and CKOUT4 divider and output buffer path is powered down. CKOUT3 and CKOUT4 outputs will be in tristate mode during powerdown. This pin has a weak pull-down. Clock Output 5. Fifth high-speed clock output with a frequency specified by FRQSEL and FRQTBL. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Clock Output 2. Differential output clock with a frequency specified by FRQSEL and FRQTBL. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Clock Output 4. Differential output clock with a frequency specified by FRQSEL and FRQTBL settings. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane.
85
DBL34
I
LVCMOS
87 88
CKOUT5- CKOUT5+
O
MULTI
92 93
CKOUT2+ CKOUT2-
O
MULTI
97 98
CKOUT4- CKOUT4+
O
MULTI
GND PAD GND PAD GND
Supply
Preliminary Rev. 0.34
11
Si5365
3. Ordering Guide
Ordering Part Number SI5365-B-GQ Package 100-Pin 14 x 14 mm TQFP Temperature Range -40 to 85 C
12
Preliminary Rev. 0.34
Si5365
4. Package Outline: 100-Pin TQFP
Figure 3 illustrates the package details for the Si5365. Table 4 lists the values for the dimensions shown in the illustration.
Figure 3. 100-Pin Thin Quad Flat Package (TQFP)
Table 4. 100-Pin Package Diagram Dimensions
Dimension A A1 A2 b c D D1 D2 e 3.85 Min -- 0.05 0.95 0.17 0.09 Nom -- -- 1.00 0.22 -- 16.00 BSC. 14.00 BSC. 4.00 0.50 BSC. 4.15 Max 1.20 0.15 1.05 0.27 0.20 Dimension E E1 E2 L aaa bbb ccc ddd 3.85 0.45 -- -- -- -- 0 Min Nom 16.00 BSC. 14.00 BSC. 4.00 0.60 -- -- -- -- 3.5 4.15 0.75 0.20 0.20 0.08 0.08 7 Max
Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MS-026, variant AED-HD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Preliminary Rev. 0.34
13
Si5365
5. Recommended PCB Layout
Figure 4. PCB Land Pattern Diagram
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Preliminary Rev. 0.34
Si5365
Table 5. PCB Land Pattern Dimensions
Dimension e E D E2 D2 GE GD X Y ZE ZD R1 R2 -- -- -- 0.15 REF 1.00 3.90 3.90 13.90 13.90 -- 1.50 REF. 16.90 16.90 MIN 0.50 BSC. 15.40 REF. 15.40 REF. 4.10 4.10 -- -- 0.30 MAX
Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Preliminary Rev. 0.34
15
Si5365
DOCUMENT CHANGE LIST
Revision 0.32 to Revision 0.33
Condensed format.
Revision 0.33 to Revision 0.34
Removed references to latency control, INC, and DEC pins. Updated Table 1, "Performance Specifications," on page 2. Changed LVTTL to LVCMOS in Table 2, "Absolute Maximum Ratings," on page 3. Added Figure 1, "Typical Phase Noise Plot," on page 4. Updated Figure 2, "Si5365 Typical Application Circuit". Updated "2. Pin Descriptions: Si5365". Updated "3. Ordering Guide" on page 12. Added "5. Recommended PCB Layout".
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Preliminary Rev. 0.34
Si5365
NOTES:
Preliminary Rev. 0.34
17
Si5365
CONTACT INFORMATION
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Preliminary Rev. 0.34

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